Editor: Rasit O. Topaloglu

Recent Topics on Modeling of Semiconductor Processes, Devices, and Circuits

Volume 1

eBook: US $44 Special Offer (PDF + Printed Copy): US $140
Printed Copy: US $119
Library License: US $176
ISBN: 978-1-60805-695-8 (Print)
ISBN: 978-1-60805-074-1 (Online)
Year of Publication: 2011
DOI: 10.2174/97816080507411110101

Introduction

The last couple of years have been very busy for the semiconductor industry and researchers. The rapid speed of production channel length reduction has brought lithographic challenges to semiconductor modeling. These include stress optimization, transistor reliability and efficient circuit design with respect to interconnects, power and leakage at the chip level. This e-book focuses on the latest semiconductor techniques devised to address these issues. It should be a useful resource for electronic engineers and semiconductor chip designers.

Foreword

Semiconductor integrated circuit design ultimately rests on foundations of modeling, analysis, and optimization. The near-term outlook for the industry includes multiple-patterning for continued pitch scaling, aggressive device mobility enhancements for continued performance scaling, and increasing intrusions of variability and reliability into the design flow. New manufacturing techniques expose effects such as electrical variability, aging, leakage, thermal variations, and noise – which are insufficiently covered by traditional device and interconnect models. Notably, electrical variability arises from multiple manufacturing steps that span lithography, embedded stressors, and rapid thermal annealing. At the same time, improved analyses and optimizations will depend heavily on the understanding and coverage of models for such new effects. To integrate the necessary models into the design cycle, new analysis, estimation, and optimization methodologies are required. For example, variability models are needed in fast chip-scale performance, yield, leakage, and thermal predictions and optimizations, as well as in decoupling capacitor planning for reduced noise. Needless to say, improved understanding of new semiconductor design effects is also needed.

The new book edited by Dr. Rasit O. Topaloglu and Dr. Peng Li targets new and critical challenges in semiconductor integrated circuit design modeling, analysis, and optimization. A key contribution of this book is its presentation of different semiconductor manufacturing models together as a package. This enables circuit designers to holistically understand multiple variability challenges, and optimize their circuits while considering all of these concerns. Furthermore, the book covers the modeling and analysis stack from transistor-level models up to chip-scale effects, thereby providing methods and insights that are not just device-specific, but that also apply at the system level. The book also introduces new manufacturing techniques and effects such as double patterning lithography, transistor aging, and process stress.

Chapter 1, on the subject of lithography, introduces the double patterning lithography process, which may become the process of choice in sub-22 nm logic designs. While there has been specialized literature in the area, it has not targeted designers as its main audience. The incorporation of this topic into the book gives valuable understanding of this technology and the design issues it may bring.

Chapter 2, on the subject of interconnect variability, introduces the impact of double patterning lithography on interconnects, and how parameter reduction techniques can be utilized with such manufacturing effects. While parameter reduction methods have been used since before the 90 nm technology node, electrical impacts from double patterning can be significant in sub-22 nm interconnects. This chapter extends the use of parameter reduction into such new contexts.

Aging has been an issue since 65 nm and is yet to be effectively managed or mitigated by designers. Chapter 3 presents aging models to target this gap. Whereas only high-voltage analog circuits were impacted in the past, in the 32 nm node even digital circuits need to be tuned for aging. This chapter in particular targets modeling aspects of both hot carrier injection and bias temperature instability.

Yield prediction methods encompass both multi-scale non-Gaussian and Pareto-based estimation techniques. The use of performance estimation techniques in conjunction with Pareto-based yield prediction has had practical impact since the 90 nm node, and will continue to be a baseline in circuit design going forward. A detailed treatment of this approach has been missing from the literature. Chapter 4, on the subject of performance estimation and yield prediction, targets this gap with phase-locked loop examples.

Stress models have been used in design since the 65 nm node. Now, however, recentlyintroduced stress sources such as through-silicon vias in 3D integration must be comprehended. Chapter 5 describes stress modeling by IBM and provides a solid review of stress modeling fundamentals, tied to electrical performance in a circuit design context.

Leakage modeling and full-chip estimation is another area of continual challenges since the 90 nm node. Chapter 6, on the subject of leakage, spans not only device-level modeling such as junction-tunnel leakage modeling, but also full-chip estimation techniques including grid-based, spectral, and projection-based statistical methods. As low-power design will remain a central methodology for the foreseeable future, this chapter is a necessary reference for designers.

Thermal analysis tools have been commercially deployed since the 90 nm node. With the introduction of 3D integration, thermal issues gain added prominence in circuit design. Chapter 7 targets thermal modeling. The Green’s function-based full-chip methods and speedup methodologies are a promising basis for scalable, accurate thermal analysis. The chapter furthermore includes comparisons with other techniques such as model order reduction and 3D alternate-direction implicit methods.

Finally, chip-package co-design has been important since the 65 nm node. Chapter 8 targets decoupling capacitor allocation using simulated annealing within a noise-driven methodology. The chapter describes spectral clustering and partitioning methods, along with localized macromodeling and sensitivity-based iterative optimizations – and is accompanied by useful industrial examples.

By bringing together recent topics in design-centric modeling, simulation, and optimization of semiconductor manufacturing effects, including new effects that designers must be aware of in sub-32 nm designs, the book is a valuable and timely contribution to researchers and practitioners in the field of integrated circuit design. Each chapter of this book is written in a way that educates the reader – from foundations and clear exposition to the latest industry status along with key references, pointers, and open problems. The book targets students, professors, as well as designers working in the industry: it provides not only introductory material, but also in-depth treatments with thought-provoking open directions for future research and development. And while it is based on technological data that will be applicable over at least the next five to ten years, its theoretical and methodological contributions will be of value over a much longer time frame.

Andrew B. Kahng, Ph.D.
Professor of Computer Science and Engineering and Electrical and Computer
Engineering
University of California, San Diego, U.S.A.


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