The last decade has been very fast-paced for the semiconductor industry and researchers. The industry has transitioned from 130 nm technology all the way down to 32 nm production already, with 22 nm process to be ready in a matter of months. The speed of feature size reduction has brought lithographic, device and interconnect design-related, as well as chipscale design challenges.
Technology scaling has been the driving force for the semiconductor industry in the past several decades. The continuing scaling in the nanometer manufacturing era has introduced profound implications. Today, manufacturing and design can no longer be considered as two independent processes; key technology characteristics and limits must be well understood in the design process. Process variation is a growing concern for devices as well as interconnects in highly scaled digital and analog designs. Furthermore, in lieu of technology and performance scaling, power consumption, device reliability, packaging, and thermal challenges must be properly addressed. Along this line, this book intends to cover the following important topics based on contributions from experts in the field.
Double patterning lithography is now used for critical layers for lithography. This topic, along with an overview of lithography in the past decade, is covered in Chapter 1. Spatial variability has drawn significant attention both in terms of devices as well as interconnects. Chapter 2 targets interconnects and impact of their variability on design. It has been found that bias temperature instability is a very important factor in temporal device reliability and needs to be considered during design. This topic is covered in Chapter 3. Accurate modeling and efficient propagation of variability information to circuit outputs has required attention. We target this topic in Chapter 4. Starting with 65 nm design, stress methods are used to further increase the device mobility. These methods are analyzed in detail in Chapter 5. Increased device leakage has made chip-level power and leakage optimization a must. Hence, Chapter 6 is devoted to leakage. Thermal issues have made chip-level thermal optimization necessary. Such effects will be more pronounced over time. These effects are analyzed in Chapter 7. Packaging considerations became part of the design phase and package design requires an elaborate interaction with the backend of the line process. Chapter 8 targets this topic. While such effects could all be analyzed separately from design in the past, they now all need to be carefully analyzed and optimized for during the chip design stage. These changes have raised designaware modeling as well as methodological and optimization challenges.
Abovementioned necessities have convinced us the need to combine recent modeling, methodology, and optimization activities in these areas into a book. We hope that this book targets these problems and offers viable and long-term solutions.
Rasit O. Topaloglu, Ph.D.
Peng Li, Ph.D.