Editor: Kunihiro Suzuki

Ion Implantation and Activation

Volume 1

eBook: US $79 Special Offer (PDF + Printed Copy): US $192
Printed Copy: US $153
Library License: US $316
ISSN: 2589-2940 (Print)
ISSN: 2215-0005 (Online)
ISBN: 978-1-60805-782-5 (Print)
ISBN: 978-1-60805-781-8 (Online)
Year of Publication: 2013
DOI: 10.2174/97816080578181130101


Ion Implantation and Activation – Volume 1 presents the derivation process of related models in a comprehensive step by step manner starting from the fundamental processes and moving up into the more advanced theories.

Ion implantation can be expressed theoretically as a binary collision, and, experimentally using various mathematical functions. Readers can understand how to establish an ion implantation database by combining theory and experimental data. The models described in this ebook can be directly related to practical experimental data with various approaches: physical, empirical or experimental. Readers can also understand the approximations, and assumptions to reach these models. Chapters in the book explain, in depth, various topics such as Pearson functions, LSS theory, Monte Carlo simulations, Edgeworth Polynomials and much more.

This book provides advanced engineering and physics students and researchers with complete and coherent coverage of modern semiconductor process modeling. Readers can also benefit from this volume by acquiring the necessary information to improve contemporary process models by themselves.


Process Modeling—the prediction of how fabrication steps affect the electrical performance of integrated circuit devices—emerged in the late 1970’s, commensurate with rapid progress in MOS scaling and Moore’s Law that predicted an exponential increase in functional density of integrated circuits. By the mid-1980’s self-aligned, silicon gate CMOS technology had overtaken earlier MOS technologies—Metal Gate and Enhancement-Depletion Mode NMOS—as the dominant digital MOS technology; a position it still holds after more than three decades.

The reasons for the dominance of self-aligned CMOS are several. Most importantly, the alignment of source and drain junctions to the gate, which is the lithographic feature that controls the scaling limit of MOS devices. Moreover, the use of a silicon gate, which can be simultaneously doped, allows the gate work function to also be controlled by the junction doping step.

Ion implantation of dopants for virtually all integrated circuit device technologies—MOS, bipolar, silicon and compound semiconductors—is unquestionably the method of choice, owing to its precision in controlling dose as well as the ability to create steep lateral and vertical profiles. The connected process steps of activating the dopant and reducing the risk of damage to the substrate material have also kept pace with scaling requirements.

This three-volume series not only addresses the physics and technology of ion implantation, activation and substrate annealing, it also provides a robust discussion of the modeling and simulation techniques that are essential for the process and device engineers to design and scale integrated circuit devices.

It is not surprising to me that Kunihiro Suzuki has prepared this comprehensive work. We first met on a very cold winter evening in Kyoto in 1988 during my one-year sabbatical leave from Stanford University. It was clear even then, in the early years of his very productive industrial career, that Suzuki-san was destined to master and expand the boundaries of process modeling. Over the ensuing quarter century, he has published cutting edge research papers in process modeling, pushed the limits of all available commercial computer-aided technology (TCAD) modeling tools and applied the result in innovative ways for the design of advanced integrated circuits.

It is certainly my great pleasure to see this excellent treatise and “tour de force” in the discussion of semiconductor doping, using ion implantation that supports ongoing engineering applications as well as informs deeper understanding of the materials and processing of advanced electronic devices.

Robert W. Dutton
Palo Alto, California