Towards a Modeling Synthesis of Two or Three-Dimensional Circuits Through Substrate Coupling and Interconnections: Noises and Parasites


Christian Gontrand

DOI: 10.2174/97816080582661140101
eISBN: 978-1-60805-826-6, 2014
ISBN: 978-1-60805-827-3

Indexed in: EBSCO.

The number of transistors in integrated circuits doubles every two years, as stipulated by Moore’s law, and this has been the driving ...[view complete introduction]
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From 2D to 3D Circuits and Systems

- Pp. 3-35 (33)

Christian Gontrand


Manufacturers introduce more and more remarkable electronic devices into the market allowing the user to surf the Internet, read e-mails, exchange files and watch (HD)TV on smart mobiles phones or PDAs (Person al Digital Assistants) set-top-boxes. These multitask devices require high performance ICs including powerful processors, huge memory capabilities. Therefore, innovative solutions have to be developed to overcome conventional 2D IC performance issues: high RC interconnect delay, thermal heating and power consumption, high integration density, small form factor, reduced packaging, increased yield and reliability, flexible heterogeneous integration and reduced overall costs. In this way, 3D stacking and high aspect ratio vertical interconnects, so-called Through Silicon Via (TSV), have recently attracted much attention to improve performance of ICs at lower cost. </p><p> Many different architectures have been proposed, but whatever the 3D approach (i.e. via first, via last…), TSVs play a key role and have to transmit a wide range of potentially high frequency signals (digital, power, analog, RF…). According to this signal diversity, it is mandatory to extract TSV characteristics, for instance its parasitic resistance, inductance, capacitance and conductance on a wide frequency range, highlighting the requirement for frequency dependent electrical models.

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