Preface

The surge of multicore processors coming into the market and on users’ desktops has made parallel computing the focus of attention once again. At this focal point of urgency and immaturity, this ebook is being put forward as a platform for immediate collection of state-of-the-art technologies in both hardware and software designs for multicore computing.

READERSHIP

It is our hope that this ebook will be of immense help to system and software engineers, including both experts and non-experts in multicore processor design and software programming. Potential readership is as follows:

1. The vast majority of software programmers who are perplexed by the rapidly increasing number of cores in a processor and by the parallel computing techniques required of them
2. Educators in the hardware and software fields, who need to catch up with multicore programming so that engineers entering the industry already have the basic art of parallel computing
3. Researchers in the parallel computing field, who need to ensure that their background knowledge in parallel computing can be adapted to multiple on-chip cores and not only distributed computing clusters

There are totally five chapters included in this ebook, which were selected from a number of submissions and reviewed thoroughly. Some of the chapters were invited from prominent groups of researchers. The chapters mainly deal with issues of thread scheduling, energy saving, and model-driven software generation and verification. In the following, we will briefly describe each of the chapters included in this issue of the ebook.

ORGANIZATION

The first chapter focuses on thread scheduling for many-core architectures that are interconnected by a 2-dimensional mesh interconnection network. It mainly evaluates thread scheduling and migration techniques through simulation. Core affinity and distance-based migration are the main criteria proposed for high-performance scheduling.

The second chapter focuses on green design with performance improvement for the cache designs in multi-core systems. It evaluates where to place the miss table in a multi-level cache hierarchy. For MPEG4 and FFT algorithms, the authors claim that cache locking at level-1 is more beneficiary than at level-2. Not only is the mean delay per task reduced significantly, but the total power consumption is also reduced drastically.

The third chapter is another chapter on green design, which focuses on how tag reduction for level-1 instruction cache can be performed in multi-core systems. A significant amount of power is saved by the proposed Tag Reduction on CMP (TRoCMP) method.

The fourth chapter is about a multi-core embedded software development framework called VERTAF/Multi-Core (VMC), which encompasses all phases of the design flow, including requirements modeling, design modeling, architecture mapping, code generation, code optimization, testing, and multi-view design repository. Automatic model-driven software development is the main goal of VMC. This is also an open-source project, which has resulted in software tools that are available for research and academia.

The fifth and final chapter in this ebook is mainly about how code can be automatically generated from SysML models that contain user-specified parallelism. All three real-world parallelism, including task parallelism, data parallelism, and data-flow parallelism (such as parallel pipeline) have been addressed in the code generator. The code generator has also been integrated as a part of the VMC framework. Currently, it supports multiple multi-core platforms including ARM 11 MPCore and Intel quad core. Libraries such as quantum platform (QP) for realizing state machines and Intel’s threading building block (TBB) for realizing parallelism are both supported in the VMC code generator.

EDITOR BIOGRAPHIES

Pao-Ann Hsiung, Ph.D., received his B.S. in Mathematics and his Ph.D. in Electrical Engineering from the National Taiwan University, Taipei, Taiwan, ROC, in 1991 and 1996, respectively. From 1996 to 2000, he was a post-doctoral researcher at the Institute of Information Science, Academia Sinica, Taipei, Taiwan, ROC. From February 2001 to July 2002, he was an assistant professor and from August 2002 to July 2007 he was an associate professor in the Department of Computer Science and Information Engineering, National Chung Cheng University, Chiayi, Taiwan, ROC. Since August 2007, he has been a full professor.

Dr. Hsiung was the recipient of the 2001 ACM Taipei Chapter Kuo-Ting Li Young Researcher for his significant contributions to design automation of electronic systems. Dr. Hsiung was also a recipient of the 2004 Young Scholar Research Award given by National Chung Cheng University to five young faculty members per year.

Dr. Hsiung is a senior member of the IEEE, a senior member of the ACM, and a life member of the IICM. He has been included in several professional listings such as Marquis' Who's Who in the World, Marquis' Who's Who in Asia, Outstanding People of the 20th Century by International Biographical Centre, Cambridge, England, Rifacimento International's Admirable Asian Achievers (2006), Afro/Asian Who's Who, and Asia/Pacific Who's Who. Dr. Hsiung is an editorial board member of the International Journal of Embedded Systems (IJES), Inderscience Publishers, USA; the International Journal of Multimedia and Ubiquitous Engineering (IJMUE), Science and Engineering Research Center (SERSC), USA; an associate editor of the Journal of Software Engineering (JSE), Academic Journals, Inc., USA; an editorial board member of the Open Software Engineering Journal (OSE), Bentham Science Publishers, Ltd., USA; an international editorial board member of the International Journal of Patterns (IJOP). Dr. Hsiung has been on the program committee of more than 60 international conferences. He served as session organizer and chair for PDPTA'99, and as workshop organizer and chair for RTC'99, DSVV'2000, PDES'2005, WoRMES’2009, and WESQA’2010. He has published more than 200 papers in international journals and conferences. He has taken an active part in paper refereeing for international journals and conferences.

His main research interests include multi-core programming, reconfigurable computing and system design, cognitive radio architecture, System-on-Chip (SoC) design and verification, embedded software synthesis and verification, real-time system design and verification, hardware-software codesign and coverification, and component-based object-oriented application frameworks for real-time embedded systems.

Yean-Ru Chen received the B.S. degree in Computer Science and Information Engineering from the National Chiao Tung University, Hsinchu, Taiwan, ROC in 2002. From 2002 to 2003, she was employed as an engineer in SoC Technology Center, Industrial Technology Research Institute, Hsinchu, Taiwan, ROC. She received the M.S. degree in Computer Science and Information Engineering from the National Chung Cheng University, ChiaYi, Taiwan, ROC in 2006. She is currently a Ph.D. candidate in Graduate Institute of Electronics Engineering of National Taiwan University, Taipei, Taiwan, ROC.

Her current research interests include model checking, SAT, SMT, safety-critical systems, network-on-chip (NoC), security-critical systems (role-based access systems) and Multi-Core embedded software.

Chao-Sheng Lin received the B.S. degree in Architecture and Urban Design from Chinese Culture University, Taipei, Taiwan, ROC, in 1998, and the M.S. degree in the Department of Computer Science and Information Engineering from National Chung Cheng University, Chiayi, Taiwan, ROC, in 2007. He is now working toward the PhD degree in the Department of Computer Science and Information Engineering at National Chung Cheng University. He has two-year working experience in software engineering and had been the vice senior software engineer in Synchronous Communication Corp. in Taiwan.

His research interests include formal verification, reconfigurable systems, and multi-core programming.

ACKNOWLEDGMENTS

We greatly appreciate the contributions from all the authors and thanks to Bentham Science Publishers for providing us such great opportunity to publish this ebook.